During the process of designing an integrated circuit (IC), a circuit designer often uses software-based graphical circuit design tools to build schematic representations of circuit designs that include symbolic representations of logical components such as inverters and other logical gates and symbolic representations of more complex functional components such as adders or Phase Lock Loops (PLLs), for example. In a hierarchical design, the schematic representations of components at a more abstract higher level of a design hierarchy hide design details shown within corresponding schematic representations at less abstract lower levels of the design hierarchy. During the design of an IC, a schematic design may be converted to a layout design, which specifies the relative positions of the geometric structures used to implement the circuit elements such as transistors, resistors, capacitors and guard rings that correspond to components of the schematic design.
In a cell-based IC design, repetitive blocks of circuitry are represented by cells that may be accessed from a design cell library using the software tool. In a cell-based hierarchical IC design, cells disposed higher in an IC design hierarchy may contain instances of other cells lower in the hierarchy. A schematic design cell higher in the hierarchy provides a graphical visual representation of the circuit functionality and hides from the user much of the detail and complexity of design cells lower in the hierarchy. A layout design comprises layout cells. A layout cell contains instances of layout cells and/or physical geometries (e.g., a metal1 stripe). The ‘Top Cell’ in a design is not instantiated within any other cell of the design. A ‘bottom cell’ in a design does not contain any instance (of other cells).
FIG. 1A is an illustrative drawing showing a representative symbolic cell (INV/Symbol) 101. FIG. 1B is an illustrative drawing showing a representative design schematic (Design/Schematic) 102 containing one instance 104 of the symbolic cell INV/Symbol 101 of FIG. 1A. FIG. 1C is an illustrative drawing showing a representative schematic cell (INV/Schematic) 108 that corresponds to the instance 104 of FIG. 1B and that contains two instances of symbolic devices, a pmos transistor device and an nmos transistor device. It will be understood that an overall circuit design may include Design/Schematic 102 or its equivalent INV/Schematic 108. However, the higher level of abstraction Design/Schematic 102 often is used to hide details shown in the lower level of abstraction INV/Schematic 108 so as so as to make the overall design more readable to the circuit designer.
A parameterized cell, or ‘pcell’, is a graphic, programmable cell that allows creation of a customized instance of the pcell each time it is placed or used in design. When instantiating a parameterized cell, a designer specifies values for parameters associated with the parameterized cell. A layout pcell is used to generate geometric structures used in a layout design. A schematic pcell is a variant of a layout pcell, which can be used in schematic designs. The use of pcells obviates the need to store individual instances of each cell. Rather, pcells are evaluated and instantiated when a design is opened, for example. The parameters of a pcell typically are used to determine the geometric dimensions of a corresponding circuit element represented by the pcell. Thus, complex geometric structures that make up circuit elements in an electronic design typically can be generated automatically based upon parameters specified by a circuit designer using a design tool. For example, a circuit designer may assemble a design that comprises multiple cells and may associate parameters with the cells. The design tool uses the parameters to generate geometric structures, represented in software data structures that correspond to actual physical structures that will be used to implement circuit elements represented by corresponding design cells.
A pcell supermaster is a type of parameterized cell that is encoded in a computer readable device and that typically is associated with a list of parameters, parameter types, parameter default values and with logic in the form of computer program code. A designer specifies parameter values of its parameters for the pcell supermaster. An automated design tool uses the logic of the pcell supermaster to generate a cell referred to as a pcell submaster that complies with the user-specified parameter values. In a typical session of an automated design tool usage, all regular cell instances of the same pcell supermaster that share the same parameter values typically also will share the same pcell submaster. Thus, instances of a regular cell within a design may be copies of a pcell submaster.
FIG. 2 is an illustrative diagram representing an data structure 200 of a parameterized cell (pcell) that is encoded in a computer readable storage device in accordance with certain prior art. The example parameterized cell data structure 200 includes a supermaster object 202 that includes computer program logic to determine geometric structures, and also includes parameter definitions and default values. Submaster objects 204-1 to 204-N are associated with the supermaster and represent different instances of the design cell that contain different unique geometries produced using code from the supermaster 202 and different unique sets of parameter values. Cell instances 206-1 to 206-N of the design cell inherit geometries from corresponding submasters 204-1 to 204-N.
More specifically, the circuit element represented by the illustrative example parameterized design cell data structure 200 of FIG. 2 is an nmos transistor. The supermaster 202 defines parameters L (length) and W (width) and includes program logic (not shown) to determine dimensions of geometric structures associated with the nmos transistor based upon parameter values. Each of the submasters 204-1 to 204-N represents a different unique instance of the nmos transistor determined with the supermaster logic using a different unique parameter value. For example, assume that a pcell supermaster 202 defines two integer parameters, namely “width” and “length”. As well, assume that pcell supermaster is associated with software logic specifying to create a rectangle corresponding to the user-specified values for a width parameter and a length parameter on some hard-coded layer within a circuit design, such as “metal1”. A designer could instantiate that pcell supermaster within a design and specify on the created instance the width parameter value to be 5 and the length parameter value to be 2. At that point, the tool application can be used to automatically create a pcell submaster 204-1 that will contain a rectangle of width=5 and length=2 on layer metal1.
It will be appreciated that often the code associated with a pcell supermaster not only can be used to create geometries but also can be used to instantiate some lower level cell.
Moreover, there exist both schematic pcell supermasters and layout pcell supermasters. The code within a schematic pcell supermaster typically creates instances of a symbolic cells and/or abstract wires. A schematic pcell submaster thus typically contains abstract wires and/or instances of symbolic cells. The code within a layout pcell supermaster typically creates layout pcell submaster instances that include instances of layout cells and/or geometries. A layout pcell submaster thus typically contains geometries and/or instances of layout cells.
Parameter expressions have been used to define parameter values. For example, a parameter ‘par1’ may be defined as ‘1+2’, e.g., par1=1+2. Hierarchical parameter values are parameter values that are passed between design cells at different hierarchy levels in an IC design hierarchy. For example, assuming that ‘pPar( )’ represents a computer program function that can be used to retrieve the value of a passed parameter, the following hierarchical parameter expression defines the value of parameter ‘par2’ as the value of a parent parameter ‘par3’ multiplied by 2: ‘par2=pPar(par3)*2’.
FIGS. 1A-1C are illustrative drawings of a design that includes an example of a ‘parent schematic cell’ (FIG. 1B) containing one ‘pPar parent instance’ of a ‘pPar parent symbolic cell’ (FIG. 1A) corresponding to a ‘pPar parent schematic cell’ (FIG. 1C) displayed on a computer device screen display in accordance with certain prior art. As used herein, a ‘pPar instance’ is an instance that has at least one parameter value defined as a function of passed parameter. As used herein, a ‘pPar parent cell’ is a cell which instantiates at least one pPar instance. A “pPar parent instance” is an instance of a pPar parent cell.
More particularly, a pPar parent instance in a hierarchical design passes a parameter to a pPar instance within a pPar cell. The pPar instance is associated with an expression within the pPar cell. The expression associated with the pPar instance uses the parameter passed to the pPar instance within the pPar cell to produces geometry structures or dimensions associated with the pPar instance. As used herein, the term ‘pPar’ signifies ‘parameter passing’ and signifies involvement in hierarchical passing of a parameter value within a hierarchical design.
It will be appreciated that the parent schematic design 102 and the schematic design cell 108 comprise computer program logic including program code and data structures encoded in a computer readable device to produce the illustrative displays.
The parent schematic design cell 102 displays a pPar parent instance symbol 104 that represents functionality of an inverter while hiding details of circuit components used to implement the inverter functionality. The parent schematic design 102 also displays user specified parameters 106. The parent schematic design 102 with its associated parameters is re-useable and may be copied multiple times within an IC design. Thus, a user need only enter the parameter values one time.
The schematic pPar parent cell 108 displays details of circuit components of an inverter. Specifically, for example, the schematic pPar parent cell 108 includes an instance of pmos transistor M0 and an instance of nmos transistor M1. The schematic pPar parent cell 108 also includes pmos instance parameters 110 and nmos instance parameters 112, which define geometric dimensions of the respective pmos and nmos devices M0 and M1 in terms of expressions that include parameters passed from the parent schematic design cell 102. For example, the instance parameter ‘nf’ is defined by the expression ‘pPar(“MULP”)’ in which the function ‘pPar(“MULP”)’ indicates that the value ‘MULP’ is passed from the parent design cell 102. An advantage of using passed parameters is that a circuit designer can specify parameters associated with a schematic design cell at a higher an IC design hierarchy and cause the design tool to pass those parameters to multiple lower level design cell instances at a lower level in the IC design hierarchy. Thus, the designer need not go through the trouble of individually specifying parameters for each schematic design instance.
Referring to FIG. 3A, there is shown an illustrative drawing of a schematic design 302 that includes a first set 303 of pPar parent instances 304-1 to 304-3 and a second set 305 of pPar parent instances 306-1 to 306-3 that correspond to the schematic pPar parent cell 108 of FIG. 1A and 1C in accordance with certain prior art. The first set of pPar parent instances 304-1 to 304-3 has different parameters than the second set of pPar parent instances 306-1 to 306-3.
FIG. 3B is an illustrative drawing representing a design layout 308 encompassing instances of transistor layout pcell supermaster produced by using a schematic driven layout generation tool to apply parameters of the schematic design 302 of FIG. 3A to the expressions shown in the instance schematic design cell 108 of FIG. 1B in accordance with certain prior art. Note that the twelve rectangles represented on FIG. 3B do not represent geometries, but rather instances of pcell supermasters. The evaluation of those instances of pcell supermasters produces pcell submasters containing the transistor geometries. In this example, a first set of layout pcell supermaster instances 310-1 to 310-3 that implement the transistors M0 and M1 correspond to pPar parent instances 304-1 to 304-3, and a second set of layout pcell supermaster instances 312-1 to 312-3 that implement the transistors M0 and M1 correspond to pPar parent instances 306-1 to 306-3. Specifically, the rectangles labeled with the symbol ‘p’ represents pmos transistor layout pcell supermaster instances, and the rectangles labeled with the symbol ‘n’ represents nmos transistor layout pcell supermaster instances. In this example pcell supermaster instance evaluation generates corresponding geometric structures, e.g. the ‘n’ and ‘p’ structures, in the first set of geometric structures 310-1 to 310-3 that have the same dimensions, and generates corresponding geometric structures in the second set 312-1 to 312-3 that have the same dimensions. However, in accordance with the parameters, dimensions of structures in the first set are generally smaller than dimensions structures in the second set. Also in this example, the schematic driven layout generation tool generates instances of ‘n’ and ‘p’ layout device pcell supermasters that are not uniformly placed within either the first layout pcell supermaster instances 310-1 to 310-3 or the second layout pcell supermaster instances 312-1 to 312-3.
A possible consequence of the non-uniform layout of the geometric structures in the different layout supermaster instances is that the transistor implementations could have different electrical characteristics, which could impact behavior of the IC design. One prior solution to the non-uniform layout problem is for the circuit designer to manually adjust the placement and routing among geometric structures. Another approach is to invoke automatic placement and routing tools to automate the placement and routing of the geometric structures. However, the manual approach typically is too complex and tedious to be practical, and the automated placement and routing does not guarantee uniform placement and routing.
Another prior solution is proposed in commonly owned U.S. Pat. No. 7,555,739 entitled, Method and Apparatus for Maintaining Synchronization between Layout Clones, which issued Jun. 30, 2009. An instance design cell within a design is ‘cloned’ such that not only do all instances of the clone have the same geometric dimensions, but they also have the same layout. Referring to the illustrative drawings of FIG. 3C, there is shown a representation of a design layout 313 encompassing instances of nmos and pmos transistors layout pcell supermaster produced by using a schematic driven layout generation tool to apply parameters of the schematic design 202 of FIG. 3A to the expressions shown in the instance schematic design cell 108 of FIG. 1C and to synchronize layout clones in accordance with certain prior art. Dashed lines 314 about the first set of geometric structures of the first layout pcell supermaster instances 310-1 to 310-3 indicate that these structures are clones within a first equivalence group. Dashed lines 316 about the second set of geometric structures of the second layout pcell supermaster instances 312-1 to 312-3 indicate that these structures are clones within a second equivalence group. The '736 patent explains that a plurality of layout clones are associated with one another within equivalence groups. Each layout clone comprises at least one figure. Relationships are tracked between equivalent figures of the plurality of layout clones. Edits made by a user to one of the layout clones in an equivalence group are propagated to the other layout clones within that equivalence group. In this manner, cloned layout designs within an equivalence group are kept in synchronization with each other despite edits to the layouts of one or more clones in the group.
While earlier approaches to achieving uniform layout generally have been acceptable, there have been shortcomings with their use. For example, synchronization of layout clones was not readily transferrable across designs. In other words, a layout of clones within an equivalence group within one design was not readily re-useable within a different design. Thus, there has been a need for the re-use of design cell layouts across different designs.